Our Plan

(Mainly introduces the planning of the open-source EDA project)

Project Plan

Prof. Yugang Bao's Plan on Open-Source Chip Project

• First Step: Open-source SoC - Provide a high-quality RISC-V open-source core and open-source SoC design verified by tape-out to the community in 3-5 years

  • RISC-V processor core IP, peripheral IP, etc.

• Second Step: Build an open-source SoC with an open-source toolchain - Gradually build an open-source SoC chip design process based on an open-source EDA toolchain, open-source IP, and open-source process library in 5-7 years

  • Gradually replace commercial tools and IP with open-source versions
  • Enable undergraduates to develop open-source chips with all open-source tools and graduate with their own chips

• Third Step: Automatically build open-source hardware with an open-source toolchain - Develop more intelligent and automated open-source tools in 10-15 years to improve design and verification efficiency

  • Form an open-source chip design ecosystem and lower the threshold for chip development

Open-Source EDA Project Planning

• First Step: In 1-2 years, iFlow: Integrate existing open-source EDA tools to form a toolchain and run through the open-source chip design

• Second Step: In 5-7 years, iEDA: Build a set of open-source EDA toolchains,

  • Replace commercial tools
  • Enable academic or teaching to develop open-source chips with all open-source tools

• Third Step: In 10-15 years, automatically design commercial mass-produced chips with an open-source toolchain

  • Develop more intelligent and automated open-source tools to improve design and verification efficiency