Softwares
Software Links
Related to iEDA
iEDA (https://gitee.com/oscc-project/iEDA): A 28nm process RTL-GDS II digital chip design platform, creating a high-quality open-source EDA infrastructure and tool platform, supporting EDA academic research, talent cultivation, and key technology incubation. Includes: iLS, iMAP, iNO, iFP, iPDN, iPL, iCTS, iTO, iRT, iDR, iSTA, iPA, iDRC and other tools, as well as basic bases such as analysis, database, evaluation, interface, operation, solver, utility.
iFlow (https://gitee.com/oscc-project/iFlow): Automated chip back-end design process, supporting 130/110/55/28nm processes, from RTL-GDS II automated back-end design full process.
iMAP (https://gitee.com/oscc-project/iMAP): FPGA process mapping tool, supporting the generation from AIG to Netlist.
iParsers (https://gitee.com/oscc-project/parser): Parsers required for EDA standard formats, including verilog, liberty, sdc, spef, sdf, vcd.
Related to AiEDA
AiEDA (https://gitee.com/ieda-iai/ai-platform): Intelligent EDA framework and toolkit, supporting framework models for multiple AI+EDA tasks, supporting flexible invocation of iEDA tools or mainstream commercial EDA tools for researching and training AI+EDA models.
iBM (https://gitee.com/oscc-project/i-bm): Construction of EDA label datasets.
AiDelay (https://gitee.com/oscc-project/delay-prediction): Delay model based on wire length fitting.
AiSTA (https://gitee.com/oscc-project/delay-calibration): Res-Unet timing learning model.
AiCap (https://gitee.com/oscc-project/pct-cap): 3D capacitance extraction network model represented by point cloud.