iEDA-Chip-001

Chip Parameters

First Tapeout: 20220202, 780 tousand gates processor chip designed by two students in the "One Chip for a Lifetime" 110nm technology, achieved a 25MHz tapeout result;

SoC Specifications:

• 5-stage, single-issue RV64I processor core
• AXI4 bus interconnect network, with two clocks designed
• Integrated UART, QSPI Flash, and ChipLink peripheral

Chip Parameters:

•Technology: 110nm
•Area: Approximately 3 ×3.5 cm
•Power Consumption: Dynamic = 48mW, Leakage = 7 mW
•Frequency: 25MHz
•Scale: 78W Gates
•Features: Supports Linux, 5-stage pipeline, ChipLink, UART, and SPI, with external board card clock

Layout Results