Research Topics To Be Studied

Research Topics To Be Studied

• Logic Synthesis (LS -)

  1. (This is LS - 01, the same as below) Logic Optimization Operator for Delay Optimization
  2. Boolean representation
  3. DSE for optimization sequence
  4. Circuit diagram partitioning
  5. Parallelization or GPU acceleration of logic optimization operators
  6. ASIC Tech Mapping algorithm oriented
  7. Physics (Delay) Aware cut learning
  8. Enhance choice - flow by applying exact synthesis with refactor and rewrite
  9. Explore structure bias for choice - based tech map
  10. Design of fast Verification technology in logic optimization and technology mapping stages
  11. Parallel verification technology
  12. Boolean matching (NPN classification)
  13. SAT Learning
  14. Learning of logic optimization operators
  15. GTech representation
  16. Functional vector sequential circuit fault simulation
      17....

• Physical Design (PD -)

  1. (This is PD - 01, the same as below) Implementation of placement legalization algorithm
  2. Incremental timing optimization algorithm
  3. Prediction of delay by layout wire length
  4. AI Macro Placement
  5. Timing driven placement
  6. Congestion driven placement
  7. New density expression (function, equation or network)
  8. Joint optimization of cell location/size and buffer
  9. Precise control of physical variables
  10. Differentiable optimization metrics (WL, Timing, Congestion)
  11. Second - order optimization method
  12. Learning of optimization direction
  13. Congestion estimation
  14. Timing estimation
  15. DRC estimation
  16. Power estimation
  17. Slew - driven CTS
  18. Joint optimization of Delay and Skew
  19. Pre - allocation of routing resources
  20. Generation of Steiner trees for nets considering routing costs
  21. Learning of multi - net resource coordinated routing cost
  22. DRC estimation
  23. Efficient routing algorithm
  24. Coupling capacitance - driven routing algorithm
  25. Timing - driven routing algorithm
  26. Modeling of routing field
      27....

• Sign - off Analysis (SO -)

  1. (This is SO - 01, the same as below) Timing correction
  2. 3D capacitance extraction
  3. GPU - accelerated equation solving
  4. Higher - order model order reduction and acceleration
  5. Machine learning fitting delay calculation
  6. Interpolation learning of unit delay
  7. Fitting of physical variables and timing
  8. Noise estimation
  9. AI buffer insertion & sizing
  10. Identifiable classification of repairable timing
  11. Numerical calculation method of field solver
  12. AI fitting RC calculation
  13. Characterization of layout data
  14. AI for RC Pattern Match
  15. Fitting of physical features and electrical variables (parasitic)
  16. IO of massive data
  17. Waveform data sampling
  18. Acceleration of Cycle - level power consumption calculation
  19. Estimation and prediction
      20....

• Physical Verification (PV -)

  1. (This is PV - 01, the same as below) Acceleration of massive data detection
  2. DFM detection
  3. DTCO, exploration of design Margin

• Other Technologies (OT -)

  1. (This is OT - 01, the same as below) Graph and layout multi - modal data representation
  2. Uncertainty measurement
  3. Partitioning algorithm
  4. Numerical calculation of PDE/ODE equations
  5. Performance acceleration
  6. LU decomposition acceleration
  7. GPU - accelerated EDA problems
  8. Microservice
  9. Cloud platform and framework
  10. DSE
  11. Application of AI large model
  12. Generation of label data
  13. Generation of power network
  14. Generation of clock tree
  15. Generation of Metal Filler
  16. Generation of IO position
  17. Generation of Design Flow
  18. Search of AI optimization algorithm (make up for the defect of most algorithms in the trade - off between exploration and utilization)
  19. AI perception and decision - making
  20. AI metric fitting and prediction
  21. AI solving PDE
  22. AI search for gradient optimization direction
  23. EDA chip design collaboration
  24. 3D Placement
      26....