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iFP - Floorplanning

iEDAAugust 8, 2024About 6 min

FP_TCL Command User Manual

Dependencies

Build

git clone --recursive
cd iEDA
mkdir build
cd build
cmake..
make

Run

cd iEDA/bin

./FP gtest.tcl

Tool Update

cd iEDA

git pull

rm -rf build

mkdir build

cd build

cmake..

make

#1. init_floorplan

**## Example: **

set DIE_AREA "0.0 0.0 2843 2843"

set CORE_AREA "150 150 2693 2693"

set PLACE_SITE HD_CoreSite

set IO_SITE IOSite

init_floorplan \

โ€‹ -die_area $DIE_AREA \

โ€‹ -core_area $CORE_AREA \

โ€‹ -core_site $PLACE_SITE \

โ€‹ -io_site $IO_SITE

#2. placeInst

The tested functions include:

  1. Placing IOCells
  2. Placing power CELLs
  3. Placing IOFILLERs
  4. Placing CORNERs

When placing the above four types, placement checks will be performed. The rules are whether they are placed according to IOSite and whether they are on the DIE BOUNDARY.

  1. Placing standard cells

**## Example: **

placeInst
-inst_name u0_clk
-llx 0
-lly 2510940
-orient E
-cellmaster PX1W

#3. placePort

This command is only for generating ports of IOPINS connected to IOCells. Ports of power CELLs do not use this interface.

**## Example: **

placePort
-pin_name osc_in_pad
-offset_x 9000
-offset_y 71500
-width 58000
-height 58000
-layer ALPA

#4. placeIoFiller

Place IOFILLERs, supporting automatic filling on four sides.

Required parameter: -filler_types The type of IOFILLER.

Optional parameters:

**## Example: **

placeIoFiller
-filler_types "PFILL50W PFILL20W PFILL10W PFILL5W PFILL2W PFILL01W PFILL001W"

โ€‹ #-prefix

โ€‹ #-edge

โ€‹ #-begin_pos

โ€‹ #-end_pos

#5. tapcell

Place tapcells and endcaps.

**## Example: **

tapcell
-tapcell LVT_FILLTIEHD
-distance 32.5
-endcap LVT_F_FILLHD1

#6. global_net_connect

Create power nets.

**## Example: **

global_net_connect
-net_name VDD
-instance_pin_name VDD
-is_power 1

global_net_connect
-net_name VDD
-instance_pin_name VDDIO
-is_power 1

global_net_connect
-net_name VSS
-instance_pin_name VSS
-is_power 0

#7. add_pdn_io

Add IOPINS for the power NET.

**## Example: **

add_pdn_io
-net_name VDD
-direction INOUT

โ€‹ #-pin_name VDD

#8. place_pdn_Port

Add PORTs for the IOPINS of the power network.

**## Example: **

place_pdn_Port
-pin_name VDD
-io_cell_name xxx
-offset_x 10
-offset_y 10
-width 100
-height 100
-layer ALPA

place_pdn_Port
-pin_name VDD
-io_cell_name xxx
-offset_x 20
-offset_y 20
-width 200
-height 200
-layer ALPA These two commands can add two ports for the VDD pin.

#9. create_grid

Generate power supply lines for standard cells and generate routing information.

**## Example: **

create_grid
-layer_name "METAL1"
-net_name_power VDD
-net_name_ground VSS
-width 0.24
-offset 0

#10. create_stripe

Generate bar-shaped power supply lines for standard cells.

**## Example: **

create_stripe
-layer_name "METAL5"
-net_name_power VDD
-net_name_ground VSS
-width 1.64
-pitch 13.12
-offset 3.895

#11. connect_two_layer

Connect the specified two layers of power supply lines.

**## Example: **

set connect1 "METAL1 METAL4"
set connect2 "METAL4 METAL5"
set connect3 "METAL5 METAL6"
set connect4 "METAL6 METAL7"
set connect5 "METAL7 METAL8"
set connect6 "METAL8 ALPA"
connect_two_layer
-layers [concat $connect1 โ€‹$connect2 โ€‹$connect3 โ€‹$connect4 โ€‹$connect5 $connect6]

  1. connect_two_layer
    -layers [concat $connect1 $connect2]
  2. connect_two_layer
    -layers "METAL1 METAL4"
    connect_two_layer
    -layers "METAL4 METAL5" The effects of sequence 1 and 2 are the same

PS: The two layers to be connected need to contain power supply lines

#12. connect_io_pin_to_pdn

Connect the Port of the IOPIN of the power NET to the power supply line in the Core. (The coordinates of the Port will be checked)

**## Example: **
connect_io_pin_to_pdn
-point_list "998 2802 915 2598"
-layer METAL1

#13. connect_pdn_stripe

connect_pdn_stripe
-point_list "2675.606 1998.707 2680.606 1998.707"
-net_name VDD
-layer ALPA
-width 100
connect_pdn_stripe
-point_list "2680.606 1892.165 2803.686 1892.165"
-net_name VDD
-layer ALPA
-width 100

#14. add_segment_via
Add vias to the power supply line.

**## Example: **

add_segment_via
-net_name VDD
-layer VIA45
-offset_x 9000
-offset_y 71500
-width 58000
-height 58000

add_segment_via
-net_name VDD
-layer VIA45
-offset_x 10000
-offset_y 81500
-width 58000
-height 58000

add_segment_via
-net_name VDD
-top_layer METAL8
-bottom_layer METAL1
-offset_x 10000
-offset_y 81500
-width 58000
-height 58000

add_segment_via
-net_name VDDIO
-top_layer METAL8
-bottom_layer METAL1
-offset_x 10000
-offset_y 81500
-width 58000
-height 58000

#15. add_segment_stripe

add_segment_stripe
-point_list "1680.606 2892.165 2803.686 2892.165 2803.686 1792.165"
-net_name VDDIO
-layer ALPA
-width 100

add_segment_stripe
-point_begin "3680.606 2892.165"
-layer_start METAL4
-point_end "4680.606 2892.165"
-layer_end METAL8
-net_name VDDIO
-via_width 100
-via_height 200

#16. read_lef

Read the lef file in the form of a string list.

**## Example: **

read_lef "../../Designs/scc011u_8lm_1tm_thin_ALPA/scc011u_8lm_1tm_th